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september 17, 1999 (version 1.3) 1 d features ? in-system programmable 3.3v proms for configuration of xilinx fpgas - endurance of 10,000 program/erase cycles - program/erase over full commercial voltage and temperature range ? ieee std 1149.1 boundary-scan (jtag) support ? simple interface to the fpga; could be configured to use only one user i/o pin ? cascadable for storing longer or multiple bitstreams ? dual configuration modes - serial slow/fast configuration (up to 15 mhz). - parallel ? low-power advanced cmos flash process ? 5 v tolerant i/o pins accept 5 v, 3.3 v and 2.5 v signals. ? 3.3 v or 2.5 v output capability ? available in pc20, so20, pc44 and vq44 packages. ? design support using the xilinx alliance and foundation series software packages. ? jtag command initiation of standard fpga configuration. description xilinx introduces the xc1800 series of in-system program- mable configuration proms. initial devices in this 3.3v family are a 4 megabit, a 2 megabit, a 1 megabit, a 512 kbit, a 256 kbit, and a 128 kbit prom that provide an easy-to-use, cost-effective method for re-programming and storing large xilinx fpga or cpld configuration bit- streams. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising cclk, data is available on the prom data (d0) pin that is connected to the fpga din pin. the fpga generates the appropriate number of clock pulses to complete the configuration. when the fpga is in slave serial mode, the prom and the fpga are clocked by an external clock. when the fpga is in express or selectmap mode, an external oscillator will generate the configuration clock that drives the prom and the fpga. after the rising cclk edge, data are available on the proms data (d0-d7) pins. the data will be clocked into the fpga on the follow- ing rising edge of the cclk. neither express nor select- map utilize a length count, so a free-running oscillator may be used. see figure 5 multiple devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family or with the xc1700l one-time programmable serial prom family. 0 xc1800 series of in-system programmable configuration proms september 17, 1999 (version 1.3) 06* preliminary product specification a figure 1: xc1800 series block diagram control and jtag interface memory serial or parallel interface d0 data (serial or parallel (express/selectmap) mode) d1 - d7 express mode and selectmap interface data address clk ce tck tms tdi tdo oe/reset ceo data 99020300 cf
r xc1800 series of in-system programmable configuration proms 2 september 17, 1999 (version 1.3) pinout and pin description table 1: pin names and descriptions pin name boundary scan order function pin description 44-pin vqfp 44-pin plcc 20-pin soic & plcc d0 4 data out d0 is the data output pin to provide data for configuring an fpga in serial mode. 40 2 1 3output enable d1 6 data out d0- d7 are the output pins to provide par- allel data for configuring a xilinx fpga in express mode. 29 35 16 5output enable d2 2 data out 42 4 2 1output enable d3 8 data out 27 33 15 7output enable d4 24 data out 9 15 7* 23 output enable d5 10 data out 25 31 14 9output enable d6 17 data out 14 20 9 16 output enable d7 14 data out 19 25 12 13 output enable clk 0 data in each rising edge on the clk input incre- ments the internal address counter if both ce is low and oe/reset is high. 43 5 3 oe/ reset 20 data in when low, this input holds the address counter reset and the data output at high impedance. 13 19 8 19 data out 18 output enable ce 15 data in when ce is high, this pin puts the device into standby mode. the data output pin is at high impedance, and the device is in low power standby mode. 15 21 10 cf 22 data out allows jtag config instruction to ini- tiate fpga configuration without power- ing down fpga. 10 16 7* 21 data in
r september 17, 1999 (version 1.3) 3 xc1800 series of in-system programmable configuration proms *programmable for serial mode only on 18512 and 1801. ceo 13 data out chip enable (ceo ) output is connected to the ce input of the next prom in the chain. this output is low when the ce and oe/reset inputs are active and the internal address counter has been in- cremented beyond its terminal count (tc) value. when the prom has been read, ceo will follow ce as long as oe/ reset is high. when oe/reset goes low, ceo stays high until the prom is brought out of reset by bringing oe/re- set high. ceo can be programmed to be either active high or active low. 21 27 13 14 output enable gnd gnd is the ground connection. 6, 18, 28 & 41 3, 12, 24 & 34 11 tms mode select the state of tms on the rising edge of tck determines the state transitions at the test access port (tap) controller. tms has an internal 50k ohm resistive pull-up on it to provide a logic 1 to the de- vice if the pin is not driven. 511 5 tck clock this pin is the jtag test clock. it se- quences the tap controller and all the jtag test and programming electronics. 713 6 tdi data in this pin is the serial input to all jtag in- struction and data registers. tdi has an internal 50k ohm resistive pull-up on it to provide a logic 1 to the system if the pin is not driven. 39 4 tdo data out this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50k ohm resistive pull-up on it to provide a logic 1 to the system if the pin is not driven. 31 37 17 v cc positive voltage supply of 3.3v for inter- nal logic and input buffers. 17, 35 & 38 23, 41 & 44 18 & 20 v cco positive voltage supply connected to the output voltage drivers. 8, 16, 26 & 36 14, 22, 32 & 42 19 pin name boundary scan order function pin description 44-pin vqfp 44-pin plcc 20-pin soic & plcc
r xc1800 series of in-system programmable configuration proms 4 september 17, 1999 (version 1.3) xilinx fpgas and compatible proms capacity device configuration bits prom xc4003e 53,984 xc18128 xc4005e 95,008 xc18128 xc4006e 119,840 xc18128 xc4008e 147,552 xc18256 xc4010e 178,144 xc18256 xc4013e 247,968 xc18256 xc4020e 329,312 xc18512 xc4025e 422,176 xc18512 xc4002xl 61,100 xc18128 xc4005xl 151,960 xc18256 xc4010xl 283,424 xc18512 xc4013xl/xla 393,632 xc18512 xc4020xl/xla 521,880 xc18512 xc4028xl/xla 668,184 xc1801 xc4036xl/xla 832,528 xc1801 xc4044xl/xla 1,014,928 xc1801 xc4052xl/xla 1,215,368 xc1802 xc4062xl/xla 1,433,864 xc1802 xc4085xl/xla 1,924,992 xc1802 xc40110xv 2,686,136 xc1804 xc40150xv 3,373,448 xc1804 XC40200XV 4,551,056 xc1804 + xc18512 xc40250xv 5,433,888 xc1804 + xc1802 xcv50 559,232 xc1801 xcv100 781,248 xc1801 xcv150 1,041,128 xc1801 xcv200 1,335,872 xc1802 xcv300 1,751,840 xc1802 xcv400 2,546,080 xc1804 xcv600 3,608,000 xc1804 xcv800 4,715,648 xc1804 + xc18512 xcv1000 6,127,776 xc1804 + xc1802 devices configuration bits 1804 4,194,304 1802 2,097,152 1801 1,048,576 18512 524,288 18256 262,144 18128 131,072
r september 17, 1999 (version 1.3) 5 xc1800 series of in-system programmable configuration proms in-system programming one or more in-system programmable proms can be daisy chained together and programmed in-system via the standard 4-pin jtag protocol as shown in figure 2 . in-sys- tem programming offers quick and efficient design itera- tions and eliminates unnecessary package handling or socketing of devices. the xilinx development system pro- vides the programming data sequence using xilinx jtag programmer software and a download cable, a third-party jtag development system, a jtag-compatible board tester, or a simple microprocessor interface that emulates the jtag instruction sequence. all outputs are 3-stated or held at clamp levels during in- system programming. external programming xilinx reprogrammable proms can also be programmed by the xilinx hw-130 device programmer. this provides the added flexibility of using pre-programmed devices in design, boundary-scan manufacturing tools, with an in-sys- tem programmable option for future enhancements and design changes. reliability and endurance xilinx in-system programmable products provide a mini- mum endurance level of 10,000 in-system program/erase cycles and a minimum data retention of 10 years. each device meets all functional, performance, and data reten- tion specifications within this endurance limit. design security the xilinx in-system programmable prom devices incor- porate advanced data security features to fully protect the programming data against unauthorized reading. table 2 shows the security setting available. the read security bit can be set by the user to prevent the internal programming pattern from being read or copied via jtag. when set it allows device erase. erasing the entire device is the only way to reset the read security bit. table 2: data security options default set read allowed program/erase allowed read inhibited via jtag erase allowed x5902 g n d v cc (a) (b) figure 2: in-system programming operation (a) solder device to pcb and (b) program using download cable
r xc1800 series of in-system programmable configuration proms 6 september 17, 1999 (version 1.3) ieee 1149.1 boundary-scan (jtag) the xc1800 family is fully compliant with the ieee std. 1149.1 boundary-scan, also known as jtag. a test access port (tap) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by ieee std. 1149.1. in addi- tion, the jtag interface is used to implement in-system programming (isp) to facilitate configuration, erasure, and verification operations on the xc1800 device. ta b l e 3 lists the required and optional boundary-scan instructions supported in the xc1800. refer to the ieee std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. table 3: boundary scan instructions instruction register the instruction register (ir) for the xc1800 is 8-bits wide and is connected between tdi and tdo during an instruc- tion scan sequence. in preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. this pattern is shifted out onto tdo (lsb first), while an instruction is shifted into the instruction register from tdi. the detailed composition of the in s t r u c t i on c aptu r e patte r n i s i l lu s trated i n f i gu r e 3 . the isp status field, ir(4), contains logic 1 if the device is currently in isp mode; otherwise, it will contain 0. the security field, ir(3), will contain logic 1 if the device has been programmed with the security option turned on; other- wise, it will contain 0. figure 3: instruction register values loaded into ir as part of an instruction scan sequence boundary scan register the boundary-scan register is used to control and observe the state of the device pins during the extest, sample/ preload, and clamp instructions. each output pin on the xc1800 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. for each output pin, the register stage nearest to tdi con- trols and observes the output state, and the second stage closest to tdo controls and observes the 3-state enable state of the pin. for each input pin, the register stage controls and observes the input state of the pin. identification registers the idcode is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. the idcode register is 32-bits wide. the idcode register can be shifted out for examina- tion by using the idcode instruction. the idcode register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v= the die version number f=the family code (50h for xc1800 family) a=the isp prom product id (06h for the xc1804) c=the company code (49h for xilinx) note: the lsb of the idcode register is always read as logic 1 as defined by ieee std. 1149.1 table 4: idcodes assigned to xc1800 devices table 4 lists the idcode register values for the xc1800 devices. boundary- scan command binary code (7:0) description required instructions bypass 11111111 enables bypass sample/ preload 00000001 enables boundary-scan sample/preload operation extest 00000000 enables boundary-scan extext operation optional instructions clamp 11111010 enables boundary-scan clamp operation highz 11111100 3-states all outputs simultaneously idcode 11111110 enables shifting out 32- bit idcode usercode 11111101 enables shifting out 32- bit usercode xc1800 specific instructions config 11101110 initiates fpga configuration by pulsing cf pin low ir(7:5) ir(4) ir(3) ir(2) ir(1:0) tdi-> 0 0 0 isp status security 0 0 1 ->tdo note: ir(1:0) = 01 is specified by ieee std. 1149.1 isp-prom idcode xc1801 05004093h xc1804 05006093h
r september 17, 1999 (version 1.3) 7 xc1800 series of in-system programmable configuration proms the usercode instruction gives access to a 32-bit user programmable scratch pad typically used to supply infor- mation about the devicess programmed contents. by using the usercode instruction, a user-programmable identifi- cation code can be shifted our for examination. this code is loaded into the usercode register during programming of the xc1800 device. if the device is blank or was not loaded during programming, the usercode register will contain ffffffffh. xc1800 tap characteristics the xc1800 family performs both in-system programming and ieee 1149.1 boundary-scan (jtag) testing via a single 4-wire test access port (tap). this simplifies system designs and allows standard automatic test equipment to perform both functions. the ac characteristics of the xc1800 tap are described as follows. tap timing figure 4 shows the timing relationships of the tap signals. these tap timing characteristics are identical for both boundary-scan and isp operations. tap ac parameters ta b l e 5 shows the timing parameters for the tap wave- forms shown in figure 4 tck tckmin tmsh tms tdi tdo tmss tdih tdozx tdov tdis tdoxz figure 4: test access port timing table 5: test access port timing parameters (ns) symbol parameter min max tckmin tck minimum clock period 100 tmss tms setup time 10 tmsh tms hold time 10 tdis tdi setup time 15 tdih tdi hold time 25 tdozx tdo float to valid delay 35 tdoxz tdi valid to float delay 35 tdov tdo valid delay 35
r xc1800 series of in-system programmable configuration proms 8 september 17, 1999 (version 1.3) controlling configuration proms connecting the fpga device with the configuration prom. ? the data output(s) of the of the prom(s) drives the din input of the lead fpga device. ? the master fpga cclk output drives the clk input(s) of the prom(s). ?the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). ? the oe/reset input of all proms is best driven by the init output of the lead fpga device. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. ?the prom ce input can be driven from either the ldc or done pins. using ldc avoids potential contention on the din pin. if the ce input of the first (or only) prom can be driven by the done output of the first fpga device, provided that done is not permanently grounded. otherwise, ldc can be used to drive ce , but must then be unconditionally high during user operation. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. ? express mode is similar to slave serial mode. the data is clocked out of the sprom one byte per cclk instead of one bit per cclk cycle. to synchronize with the fpga the first byte of data is valid 20ns before the second rising edge of cclk and then on every consecutive cclk thereafter. note: when programming in express mode, to accommodate the 4us set-up time on the init pin of the spartan fpga, the first line of the configuration stream must not be placed higher than the 3c byte address of the prom. initiating fpga configuration the xc1800 devices incorporate a pin named cf that is controllable through the jtag config instruction. execut- ing the config instruction through jtag will pulse the cf low for 300-500ns, which will reset the fpga and initiate configuration. the cf pin must be connected to the program pin on the fpga to use this feature. selecting configuration modes the xc1800 accommodates serial and parallel methods of configuration. the configuration modes are selectable through a user control register in the xc1800 device. this control register is accessible through jtag, using the xilinx jtag programmer software. fpga master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are estab- lished by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master serial mode, the fpga automatically loads the con- figuration program from an external memory. xilinx proms are designed for compatibility with the master serial mode. upon power-up or reconfiguration, an fpga enters the master serial mode whenever all three of the fpga mode- select pins are low (m0=0, m1=0, m2=0). data is read from the prom sequentially on a single data line. synchroniza- tion is provided by the rising edge of the temporary signal cclk, which is generated during configuration. master serial mode provides a simple configuration inter- face. only a serial data line and two control lines are required to configure an fpga. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function din pin on the fpga is used only for configuration, it must still be held at a defined level during normal operation. the xilinx fpga families take care of this automatically with an on- chip default pull-up resistor. programming the fpga with counters unchanged upon completion when multiple fpga-configurations for a single fpga are stored in a prom, the oe/reset pin should be tied low. upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. since the oe/reset pin is held low, the address counters are left unchanged after configuration is com- plete. therefore, to reprogram the fpga with another pro- gram, the done line is pulled low and configuration begins at the last value of the address counters. this method fails if a user applies oe/reset during the fpga configuration process. the fpga aborts the config- uration and then restarts a new configuration, as intended, but the prom does not reset its address counter, since it never saw a high level on its oe input. the new configura- tion, therefore, reads the remaining data in the prom and interprets it as preamble, length count etc. since the fpga is the master, it issues the necessary number of cclk pulses, up to 16 million (2 24 ) and done goes high. how- ever, the fpga configuration will be completely wrong, with potential contentions inside the fpga and on its output pins. this method must, therefore, never be used when there is any chance of external reset during configuration. cascading configuration proms for multiple fpgas configured as a daisy-chain, or for fpgas requiring larger configuration memories, cascaded proms provide additional memory. multiple xc1800 devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all xc1800 devices in the chain are
r september 17, 1999 (version 1.3) 9 xc1800 series of in-system programmable configuration proms interconnected. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and disables its data line. the second prom recognizes the low level on its ce input and enables its data output. see figure 5 . after configuration is complete, the address counters of all cascaded proms are reset if the prom oe/reset pin goes low. to reprogram the fpga with another program, the done line goes low and configuration begins where the address counters had stopped. in this case, avoid contention between data and the configured i/o use of din.
r xc1800 series of in-system programmable configuration proms 10 september 17, 1999 (version 1.3) figure 5: (a) master serial mode (b) virtex select map mode (c) spartan xl express mode program din cclk init done first prom data ceo clk ce optional slave fpgas with identical configurations vcc fpga (low resets the address pointer) vcc v cc v cco cascaded prom data clk ce optional daisy-chained fpgas with different configurations oe/reset d out modes vcco cf m0 m1 m2 program virtex select map busy cs write init d0-d7 cclk done 3.3v v cc v cco clk virtex select map mode d0-d7 ce oe/reset xc18xx nc cf 3.3v external osc vcc vcco ceo 4.7k 4.7k i/o* m0 m1 cs1 program spartan xl dout done init xc18xx ceo ce oe/reset spartan xl express mode master serial mode oe/reset 8 cf clk v cc v cco vcc vcco d0-d7 d0-d7 vcc cclk m0 m1 cs1 program optional daisy-chained spartan xl dout done init d0-d7 cclk vcc 4k 8 to additional optional daisy-chained devices to additional optional daisy-chained devices cclk i/o* 4.7k *cs and write must be pulled down to be used as i/o. one option is shown.
r september 17, 1999 (version 1.3) 11 xc1800 series of in-system programmable configuration proms 5v tolerant i/os the i/os on each re-programmable prom are fully 5v tol- erant even through the core power supply is 3.3 volts. this allows 5v cmos signals to connect directly to the prom inputs without damage. in addition, the 3.3v v cc power supply can be applied before or after 5v signals are applied to the i/os. in mixed 5v/3.3v/2.5v systems, the user pins, the core power supply (v cc ), and the output power supply (v cco ) may have power applied in any order. this makes the prom devices immune to power supply sequencing issues. reset activation on power up, oe/reset is held low until the xc1800 is active (1ms) and able to supply data after receiving a cclk pulse from the fpga. oe/reset is connected to an exter- nal resistor to pull oe/reset high releasing the fpga init and allowing configuration to begin. oe/reset is held low until the xc1800 voltage reaches the operating voltage range. if the power drops below 2.0 volts, the prom will reset. standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high imped- ance state regardless of the state of the oe input. jtag pins tms, tdi and tdo can be 3-state or high. note: tc = terminal count = highest address value. tc+1 = address 0. table 6: truth table for prom control inputs control inputs internal address outputs oe/reset ce data ceo i cc low low if address < tc: increment if address > tc: dont change active 3-state high low active reduced high low held reset 3-state high active low high held reset 3-state high standby high high held reset 3-state high standby
r xc1800 series of in-system programmable configuration proms 12 september 17, 1999 (version 1.3) absolute maximum ratings notes 1: maximum dc undershoot below gnd must be limited to either 0.5v or 10ma, whichever is easier to achieve. during transitions, the device pins may undershoot to -2.0v or overshoot to +7.0v, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200ma. 2: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. recommended operating conditions quality and reliability characteristics symbol description value units v cc supply voltage relative to gnd -0.5 to +4.0 v v in input voltage with respect to gnd -0.5 to +5.5 v v ts voltage applied to 3-state output -0.5 to +5.5 v t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in.) +260 c t j junction temperature +150 c symbol parameter min max units v ccint commercial internal voltage supply (t a = 0 c to +70 c) 3.0 3.6 v industrial internal voltage supply (t a = -40 c to +85 c) 3.0 3.6 v v cco supply voltage for output drivers for 3.3v operation 3.0 3.6 v supply voltage for output drivers for 2.5v operation 2.3 2.7 v v il low-level input voltage 0 0.8 v v ih high-level input voltage 2.0 5.5 v v o output voltage 0 v cco v symbol description min max units t dr data retention 10 - years n pe program/erase cycles (endurance) 10,000 - cycles v esd electrostatic discharge (esd) 2,000 - volts
r september 17, 1999 (version 1.3) 13 xc1800 series of in-system programmable configuration proms dc characteristics over operating conditions * 1801/18512/18256/18128 only, cascadable **1801/18512/18256/18128 only, non-cascadable symbol parameter test conditions min max units v oh high-level output voltage for 3.3 v outputs i oh = -4 ma 2.4 v high-level output voltage for 2.5 v outputs i oh = -500 m a 90% v cco v v ol low-level output voltage for 3.3v outputs i ol = 8 ma 0.4 v low-level output voltage for 2.5v outputs i ol = 500 m a0.4v i cca supply current, active mode at maximum frequency 30.0 ma i ccs1 supply current, standby mode 1 2.0 ma i ccs2* supply current, standby mode 2 300 m a i ccs3** supply current, standby mode 3 100 m a i ilj jtag pins tms, tdi, and tdo v cc = max v in = gnd -100 m a i il input leakage current v cc = max v in = gnd or v cc -10.0 10.0 m a i ih input & output high-z leakage current v cc = max v in = gnd or v cc -10.0 10.0 m a c in & c out input and output capacitance v in = gnd f = 1.0 mhz 10.0 pf
r xc1800 series of in-system programmable configuration proms 14 september 17, 1999 (version 1.3) . ac characteristics over operating conditions notes: 1. ac test load = 50 pf 2. float delays are measured with 5 pf ac loads. transition is measured at +/- 200mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0 v and v ih = 3.0 v. reset/oe ce clk data 1 t ce 2 t oe t lc 7 9 t sce t sce t hce t hoe 11 t cac t oh t df 5 t oh 4 4 3 9 10 t hc 8 99020801 t cyc 6 symbol description min max units 1t oe oe to data delay 30 ns 2t ce ce to data delay 45 ns 3t cac clk to data delay 45 ns 4t oh data hold from ce , oe, or clk 0 ns 5t df ce or oe to data float delay 2 50 ns 6t cyc clock periods 67 ns 7t lc clk low time 3 25 ns 8t hc clk high time 3 25 ns 9t sce ce setup time to clk (to guarantee proper counting) 25 ns 10 t hce ce hold time to clk (to guarantee proper counting) 0 ns 11 t hoe oe hold time (guarantees counters are reset) 25 ns
r september 17, 1999 (version 1.3) 15 xc1800 series of in-system programmable configuration proms ac characteristics over operating condition when cascading notes: 1. ac test load = 50 pf 2. float delays are measured with 5 pf ac loads. transition is measured at +/- 200mv from steady state active levels. 3. characterized but not 100% tested. 4. all ac parameters are measured with v il = 0.0 v and v ih = 3.0 v. symbol description min max units 12 t cdf clk to data float delay 2, 3 50 ns 13 t ock clk to ceo delay 3 30 ns 14 t oce ce to ceo delay 3 35 ns 15 t ooe reset /oe to ceo delay 3 30 ns clk data ce 15 t ooe ceo first bit last bit t oce 13 t ock 12 t cdf 99020800 14 t oce 14 reset/oe
r xc1800 series of in-system programmable configuration proms 16 september 17, 1999 (version 1.3) ordering information valid ordering combinations marking information revision control xc1804vq44c xc1802vq44c xc1801so20c xc18512so20c xc18256so20c xc18128so20c xc1804pc44c xc1802pc44c xc1801pc20c xc18512pc20c xc18256pc20c xc18128pc20c xc1804vq44i xc1802vq44i xc1801so20i xc18512so20i xc18256so20i xc18128so20i xc1804pc44i xc1802pc44i xc1801pc20i xc18512pc20i xc18256pc20i xc18128pc20i date version revision 2/9/99 1.0 first publication of this early access specification 8/23/99 1.1 edited text, changed marking, added cf and parallel load 9/1/99 1.2 corrected jtag order, security and endurance data. 9/16/99 1.3 corrected selectmap diagram, control inputs, reset polarity. added jtag and cf description, 256 kbit and 128 kbit devices. xc1804 vq44 c operating range/processing c= commercial (t a = 0 to +70 c) i = industrial (t a = C40 to +85 c) package type vq44=44-pin plastic quad flat package pc44=44-pin plastic chip carrier so20=20-pin small-outline package pc20=20-pin plastic leaded chip carrier device number xc1804 xc1802 xc1801 xc18512 xc18256 xc18128 xc1804 vq44 c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = C40 to +85 c) package type vq44=44-pin plastic quad flat package pc44=44-pin plastic, leaded chip carrier device number xc1804 xc1802 1801 s c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = C40 to +85 c) package type s=20-pin small-outline package j=20-pin plastic leaded chip carrier device number xc1801 xc18512 xc18256 xc18128 20-pin package 44-pin package

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